|
Time
|
Topic
|
Speaker
|
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13:00-13:30
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报到 Registration
|
|
|
13:30-13:35
|
开幕词
Opening
|
林志明，晶心科技总经理
Frankwell Lin, President
Andes Technology
|
|
13:35-14:05
|
Keynote
|
包云岗博士，中国开放指令生态（RISC-V）联盟秘书长暨中科院计算所研究员
Dr. Yungang Bao, Professor
Institute of Computing Technology, Chinese
Academy of Sciences
|
|
14:05-14:30
|
RISC-V是领先潮流的芯片主架构
RISC-V Leads in CPU Architecture for SoC Design
|
林志明，晶心科技总经理
Frankwell Lin, President
Andes Technology
|
|
14:30-15:10
|
Powering RISC-V SoCs with 1 to 1,000s AndesCores
|
苏泓萌博士，晶心科技 技术长兼执行副总经理
Dr. Charlie Su, CTO & EVP
Andes Technology
|
|
15:10-15:30
|
茶歇Tea Break
|
|
15:30-15:55
|
Fast Start into RISC-V for AIoT with A+ Core |
石佳弘，晶心科技解决方案架构工程处副处长
John Shih, Deputy Director of Solution
Architecture Division
Andes Technology
|
|
15:55-16:25
|
Faraday RISC-V based ASIC Solution for Edge AI
and IoT SoCs
|
Kenneth Lu, Marketing Manager
Faraday智原科技
|
|
16:25-16:55
|
Security Enclave
Based on RISC-V
|
Christopher
Beaver, Field Application Engineer for Embedded Security Products
Silex Insight
|
|
16:55-17:25
|
Making RISC-V The Most Secure Platform |
Cesare Garlati, CEO
Hex Five Security, Inc.
|
|
17:25-
|
Q&A / Lucky Draw
|
|
|
