会议展览
中国集成电路设计业2018年会暨珠海集成电路产业创新发展高峰论坛(ICCAD 2018)

2018年11月29-30日,珠海

王中风

用于高速网络通信的先进纠错编码

Advanced FEC Codes for High-Speed Networking

 

  演讲人

王中风

教授/博导

国家千人计划特聘专家

IEEE Fellow

南京大学微电子学院副院长

Zhongfeng Wang, Professor/PhD Advisor

Distinguished Expert from the State’s 1000-Talent Plan, IEEE Fellow

Associate Dean of School of Microelectronics at Nanjing University

 

演讲人简历

王中风博士是国家中组部“千人计划”特聘专家,2015年因在FEC设计与VLSI实现方面的突出贡献被评为IEEE Fellow,现任南京大学电子科学与工程学院特聘教授、博导。 王中风博士早年凭自学考入清华大学,本科获准提前毕业,相继在自动化系获得学士和硕士学位。2000年他从美国明尼苏达大学电子与计算机工程系获得博士学位。 他先后任职于国家半导体公司(National Semiconductor Corp.),俄勒冈州立大学(Oregon State University)电子与计算机学院,以及美国博通公司(Broadcom Corp., 曾经担任博通公司技术副总监。他同时担任过美国科罗拉多大学,中国科学技术大学以及南京大学的兼职教授。王博士是超大规模集成电路 (VLSI) 设计领域里的国际知名专家,在国际会议和期刊上发表过150余篇学术论文并两次获得最佳论文奖。 此外他拥有数十项美国专利和发明,并编著专辑“VLSI”一部。在现有统计记录中,他是全球第一位在IEEE VLSI Systems会刊上有五篇论文位列年度下载次数前20名的作者。在俄勒冈州立大学执教期间(2003-2007),王中风博士作为项目负责人或联合负责人承担过多项美国国家科学基金(NSF)和美国太空总署(NASA)的科研项目。在博通公司工作期间,他参与了近十款高速网络通信芯片的设计,创造了多项行业领先的技术和产品。 同时他参与了多项工业国际标准的制订工作,他的有关技术提案已经被IEEE十余种高速网络通信标准所采纳。王中风博士多次担任国际一流学术刊物编委职务并长期在IEEE等国际会议中担任技术委员会委员(或主席),分会主席及评审委员等。目前,王中风博士是IEEE电路与系统协会下属的两个技术委员会:1)超大规模集成电路系统与应用(VTA-TC2)通信电路与系统(CASCOM)的专家组成员,他同时也是IEEE信号处理协会下属的信号处理系统设计与实现(DISPS)专家组的顾问委员。

 

Dr. Zhongfeng Wang received both Bachelor and Master degrees from Tsinghua University, Beijing. He obtained the Ph.D. degree from the University of Minnesota, Minneapolis. He is currently a Distinguished Professor at Nanjing University from the State's 1000-Talent Plan. Previously he worked for Broadcom Corporation, California, from 2007 to 2016, as a leading VLSI architect. Before that, he was an Assistant Professor at Oregon State University. Even earlier he was working for National Semiconductor Corporation. He has also held Professor Adjunct positions at a few universities including the University of Colorado and the University of Science and Technology of China.

 

Dr. Wang is a world-recognized expert on Low-Power High-Speed VLSI Design for Signal Processing Systems. He has published over 150 papers with two best paper awards received in the IEEE Circuits and Systems (CAS) society. He has edited one book “VLSI” and filed over forty U.S. patent applications and disclosures. In the current record, he has had five papers ranked among top 20 most downloaded manuscripts in IEEE Trans. on VLSI Systems. In the past, he has served as Associate Editor for IEEE Trans. on CAS-I, CAS-II, and VLSI Systems for multiple terms. He has been serving in three technical committees in IEEE CAS society and Signal Processing society. In 2013, he served in the Best Paper Award selection committee for the IEEE CAS society. Moreover, he has contributed significantly to the industrial standards, specifically IEEE 100G and 400G Ethernet, as well as ITU-T 100G and B100G Optical Transport Network (OTN) standards. So far, his technical proposals have been adopted by more than ten international network standard specs. In 2015, He was elevated to Fellow of IEEE for contributions to VLSI design and implementation of FEC coding. His current research interests include Low Power/High Speed VLSI Design for Digital Communications and Machine Learning.

报告摘要:

在这次报告中,我们首先讨论标准和非标准的用于高速网络通信系统的前向纠错码,特别是用于高速以太网和光传输网络(OTN)系统的前向纠错码。随后,我们将集中讨论设计和实现一个特定的超强FEC码。 它的性能接近Shannon极限, 40nm工艺下ASIC设计的吞吐量可以达100Gbps以上。

 

In this talk, we first discuss standard and non-standard FEC codes used for high-speed networking systems, specifically FEC codes for high-speed Ethernet and Optical Transport Network (OTN) systems. Thereafter, we will focus on design and VLSI implementation of a specific Super-FEC code. The code achieves near Shannon limit performance and the ASIC implementation under 40nm technology can achieve a worst-case throughput over 100Gbps.


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