周军

机遇与挑战:近阈值/亚阈值数字集成电路设计

Opportunities and Challenges: Near/Sub-Threshold Digital IC Design

 

  演讲人

周军

教授/博导,2017年国家青年千人计划入选者

电子科技大学通信与信息工程学院物联网

专用集成电路与系统研究团队负责人

Jun Zhou, Professor, Recipient of 2017 Thousand Young

                    Talents Award, Director of IoT Integrated Circuits &

                    Systems Research Group, School of Communication and Information 

                   Engineering, University of Electronic Science and Technology of China

 

演讲人简历

周军,电子科技大学教授/博导,2017国家青年千人计划入选者,IEEE高级会员,博士毕业后曾先后在欧洲校际微电子研究中心IMEC、新加坡微电子研究院工作8,任项目负责人、博士生导师,专注于低功耗数字集成电路与系统研究,面向物联网、智能传感、智能穿戴、人工智能等新兴应用。担任多个国际知名会议的技术委员会委员和分会场主席,包括ISCAS 2017技术委员会委员和分会场主席、ICCD 2017技术委员会委员、A-SSCC 2016技术委员会委员和分会场主席等,同时担任JSSCTCAS-I/II, TVLSI等多个国际知名期刊的长期评委。

 

Dr. Jun Zhou is a Professor at the University of Electronic Science and Technology of China (UESTC). He is a recipient of 2017 Thousand Young Talents Award and a senior member of IEEE. Before joining UESTC, he has worked at IMEC and Institute of Microelectronics (Singapore) as project leader and PhD supervisor for over 8 years with a research focus on ultra-low power digital integrated circuits and systems for emerging applications such as IoT, intelligent sensing, wearable devices and artificial intelligence. He is serving/has served as TPC member/session chairs in a number of prestigious conferences including ISCAS 2017, ICCD 2017 and A-SSCC 2016. He is also a long-term reviewer for prestigious journals such as JSSC, TCAS-I/II and TVLSI.

 

报告摘要:

物联网、智能传感,智能穿戴等新兴应用要求设备具有智能化、微型化、低功耗三个特点。其中,智能化需要更高的数字处理能力,微型化限制了电池的尺寸,二者与低功耗的要求矛盾。为了化解这个矛盾,研究超低功耗数字集成电路成为一个必然。作为实现超低功耗数字集成电路的一种重要技术,近阈值/亚阈值设计近年来受到了国际学术界和工业界的广泛关注。该报告将分析目前近阈值/亚阈值数字集成电路设计面临的机遇和挑战,并结合电路,架构,应用等多个角度,探讨解决方法和未来的研究方向。

 

Emerging applications such as IoT, Intelligent Sensor and Wearable devices require the device to be intelligent, miniaturized, and low power. However, intelligence requires powerful signal processing capability and miniaturization limits the size of battery, which are contradictory to the requirement of low power. To address this issue, ultra-low power digital IC design becomes a must. As a promising technology for achieving ultra-low power, near/sub-threshold design has attracted wide attention in recent years. This talk will introduce the opportunities and challenges of near/sub-threshold digital IC design. It will also discuss the potential solutions and future research directions through the design hierarchy, including circuit, architecture and application.


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